1. Field of the Invention
The present invention relates to a microcomputer, and more particularly, to an interrupt control circuit of the microcomputer.
2. Description of Related Art
In a conventional microcomputer, an interrupt request issuing unit or section is fixedly connected to a central processing unit (CPU) and hence there is no flexibility. An example of the conventional microcomputer 100 is shown in FIG. 1. The microcomputer 100 includes a central processing unit (CPU) 2, a memory 4 having tables 4-1 to 4-3, an interrupt control circuit 5, two peripheral sections 10 and 11 such as a timer and a serial interface, a terminal 12 for receiving an interrupt request from an external unit and a bus 30, for instance. The interrupt control circuit 5 includes a priority determining circuit 6 and three interrupt flag registers 7 to 9. The bus 30 connects between the CPU 2 and each of the memory 4, the interrupt flag registers 7 to 9, and the peripheral sections 10 and 11. The peripheral sections 10 and 11 and the terminal 12 are connected to the interrupt flag registers 7 to 9 via interrupt request lines 39, 40 and 41, respectively, and the interrupt flag registers 7 to 9 are connected to the priority determining circuit 6 via pairs of a flag state line and a flag clear line 33 and 36, 34 and 37, and 35 and 38. The priority determining circuit 6 is connected to the CPU 2 via an interrupt line 31 and an interrupt reception line 32 and selects and outputs to the CPU 2 an interrupt having the highest priority level from among a plurality of interrupts stored in the interrupt flag registers 7 to 9 when the interrupts conflicts with each other. The tables 4-1 to 4-3 in the memory 4 are respectively provided for the interrupt flag registers 7 to 9 and each of the tables stores a start address of a program (subroutine) to be executed by the CPU 2 when the interrupt stored in the corresponding interrupt flag register is selected.
The interrupt flag registers 7 to 9 are normally kept in the reset state of "0" and are set to "1" in response to the interrupt request signals-via the interrupt request lines 39 to 41, to inform the interrupts to the priority determining circuit 6 via the flag state lines 33 to 35, respectively. Each of the interrupt flag registers 7 to 9 has a vector address to read out a start address from the corresponding tables 4-1 to 4-3 in the memory 4. Also, the interrupt flag registers 7 to 9 are reset in response to the flag clear signal via the flag clear lines 36 to 38, respectively. Further, the interrupt flag registers 7 to 9 are allocated with predetermined priority levels, e.g., the priority levels are higher in order of the interrupt flag register 7, the interrupt flag register 8 and the interrupt flag register 9. The priority determining circuit 6 determines the interrupt request signal having the highest priority level from among currently issued interrupt request signals to output to the CPU 2 as the interrupt signal via the interrupt line 31 when two or more interrupt flag registers are set, and outputs the interrupt signal to the CPU 2 when the single interrupt flag register is set.
Next, an operation of the microcomputer 100 will be described below.
First, the case where a single interrupt request signal is issued will be described below taking as an example the interrupt request signal issued from the peripheral section 10. When the interrupt request signal via the interrupt request line 39 is set to the active state of "1" during a predetermined period of time by the peripheral section 10, the interrupt flag register 7 is set to "1", so that the flag state signal via the flag state line 33 of "1" is outputted to the priority determining circuit 6. The priority determining circuit 6 detects the flag state signal via the flag state line 33 of "1" to supply the interrupt signal via the interrupt line 31 of "1" to the CPU. In response to the interrupt request signal via the interrupt line 31 of "1", the CPU 2 issues the interrupt reception signal via the interrupt reception line 32 of "1" during a predetermined period of time to the priority determining circuit 6. At the same time the CPU 2 executes an interrupt reception program to read out the start address from the table 4-1 corresponding to the vector address of the flag register 7 and executes an interrupt processing program (not shown) in accordance with the start address. In response to the interrupt reception signal via the interrupt reception line 32, the priority determining circuit 6 resets the interrupt signal via the interrupt line 31 to "0" and holds the flag clear signal via the flag clear line 36 in the state of "0" during a predetermined period of time, so that the interrupt flag register 7 is reset to "0". As a result, the interrupt processing is completed.
Next, the case where two interrupt request signals are issued at a time will be described below, taking as an example the interrupt request signals supplied from the peripheral section 11 and the terminal 12. Assume that the interrupt request signal via the interrupt request line 41 and the terminal 12 at the same time when the interrupt request signal via the interrupt request line 40 is issued from the peripheral section 11. The interrupt flag registers 8 and 9 are set to "1" in response to the interrupt request signals via the interrupt lines 40 and 41, respectively, so that the flag state signals via the interrupt lines 34 and 35 are set to "1". The priority determining circuit 6 determines which of the flag state signals via the interrupt lines 34 and 35 has a higher priority level. As a result, the priority determining circuit 6 selects the flag state line 34 corresponding to the peripheral section 11 and issues the interrupt signal via the interrupt line 31 of "1" to the CPU based on the flag state signal via the flag state line 34. In this case the flag state signal via the flag state line 35 is kept in the state of "1", i.e., in the active state. The CPU 2 reads out a start address from the table 4-2 based on the vector address of the flag register 8 and executes an interrupt processing program (not shown) in accordance with the start address, as described above. The CPU 2 also issues the interrupt reception signal via the interrupt reception line 32 of "1" during the predetermined period of time to the priority determining circuit 6 in response to the interrupt signal via the interrupt line 31 of "1". In response to the interrupt reception signal via the interrupt line 32, the priority determining circuit 6 resets the interrupt signal via the interrupt line 31 to "0" and holds the flag clear signal via the flag clear line 37 in the state of "1" during the predetermined period of time, so that the interrupt flag register 8 is reset to "0". As a result, the interrupt processing is completed for the interrupt request signal via the interrupt request line 40. Because the flag state signal via the flag state line 35 is kept in the state of "1", the interrupt signal via the interrupt line 31 is issued from the priority determining circuit 6 to the CPU 2 based on the flag state signal via the flag state line 35 after the interrupt processing for the interrupt request signal via the interrupt request line 40 is completed. Then the similar operation is performed and the interrupt processing for the interrupt request signal via the interrupt request line 41 having a lower priority level is also completed.
However, in an application system in which such a microcomputer is utilized, all the peripheral sections built in the microcomputer are not always used. Ones of the peripheral sections necessary for the application are selected and used. Therefore, the hardware for interrupt processing of the peripheral sections unnecessary for the application is wasted. In addition, a user demands a microcomputer in which peripheral sections optimal to the application system are built. As a result, if a plurality of interrupts are necessary, it is demanded that the priority levels of the interrupts be optimized for the application system.